In the fabrication of integrated circuits, it is conventional to produce a multiplicity of identical integrated circuits in a single large wafer of semiconductor crystal with the individual identical circuits numbering into the thousands and arranged in a matrix of rows and columns throughout the crystal. Before the individual integrated circuit elements are severed from each other for further assembly into the marketed product, it is conventional to test each circuit to insure that it operates within performance limits. This has typically been done by aligning the matrix in a test fixture (such as a Teledyne TAC PR-100 wafer prober) which moves the wafer up and down into contact with a plurality of electrical leads which probe the circuit terminal pads. Each time the wafer is moved up or down it is indexed one circuit space to the right or left or across until the test head has probed each circuit in a row or column.
In this test process, the edge of the wafer is typically detected using a mechanical edge detector which is positioned to contact the wafer each time it is raised in position for operation of the test head. Failure of the probe to make mechanical contact with the wafer is an indication of the passage of the edge and causes the test system to alter its indexing motion in some predetermined manner such as by moving to the next row.
The gauging of edge position by mechanical contact, as has been practiced in the past, has led to damage to the wafer in particular circuit areas where the edge detecting probe strikes the wafer on its way up for engagement with the test head. Various forms of noncontact gauging might be employed but there are environmental and placement problems to be overcome with such devices. Capacitor gauging provides one alternative, but adds the difficulty of interference with the circuit test circuitry from the active gauging probe as well as error effects resulting from the necessary use of a very small capacitance variation between conditions of wafer and no wafer.